| Degree
| Institute
| Year
| Board/University
| Percentage/CGPA
| Remarks
|
AISSE
(Class 10)
| Kendriya Vidyalaya
Jorhat Assam
| 1995
| CBSE
| 83.2
| -
|
AISSCE
(Class 12)
| Kendriya Vidyalaya
Jorhat Assam
| 1997
| CBSE
| 80.2
| -
|
B.E
(Dept. of CSE)
| REC Durgapur
| 2001
| Burdwan
| 79.7(1st Hons)
| 3rd in the University
|
| MS(by Research)
| IIT Kharagpur
(Dept. of EE)
| 2004
| -
| 10.0/10.0
| Institute Highest CGPA of the year 2003-04
|
| PhD
| IIT Kharagpur
(Dept. of CSE)
| 2008
| -
| -
| -
|
Experiences
|
|
July 2001-December 2001:
Development of Algorithms and Software for "Economic Generation Scheduling" for CESC Kolkata (a consultancy project under taken by SRIC, IIT Kharagpur)
January 2002-June 2008:
Research Consultant for Advanced VLSI Design Laboratory (Testing), IIT Kharagpur
May 2005--May 2006:
Research Consultant for a consultancy project undertaken by IIT Kharagpur and National Semiconductor
Corp. USA on "Development of Template based CAD tools for Placement and Routing of Test Chips (TRET)"
June 2008-November 2008 :
Senior Lecturer, Department of CSE IIT Guwahati
November 2008 - February 2014:
Asst. professor, Department of CSE IIT Guwahati
March 2014-till date:
Asso. professor, Department of CSE IIT Guwahati
June 2018-till date:
Visiting Asso. professor, Department of EECS, IIT Bhilai
|
| Serial No. |
Course Name |
UG/PG |
No. of Times Taughts |
| 1
| Theoretical Foundation of Computer System
| PG
| 2
|
| 2
| CAD for VLSI
| PG+UG
| 2
|
| 3
| Systems Programming Lab.
| UG
| 8
|
| 4
| Systems Software Lab.
| UG
| 8
|
| 5
| VLSI Design, Test and Verification
| UG+PG
| 3
|
| 6
| Compilers
| UG
| 2
|
| 7
| Compilers Lab.
| UG
| 2
|
| 8
| Digital Logic and Computer Architecture
| Minor UG (Minor)
| 1
|
| 9
| Computer Organization and Architecture
| UG
| 4
|
| 10
| Digital Design
| UG
| 4
|
|
|
1: NPTEL web course "VLSI Design Verification and Test"
2: NPTEL video course "Design Verification and Test of Digital VLSI Circuits"
3: Pedagogical Methods "Computer Organization and Architecture"
4: MOOCS course "VLSI Design Verification and Test" (2016)
5: MOOCS course "Computer Organization and Architecture: A Pedagogical Aspect" (2018)
6: MOOCS course "Optimization Techniques for Digital VLSI Design" (2018)
7: MOOCS course "Embedded Systems--Design Verification and Test" (2018)
|
|
|
Academic Projects:
1. Algorithms and Software for solving Linearly Separable and Inseparable Problems of Pattern Classification
( Final Year Project for the Degree: Bachelor of Engineering ).
2. Algorithms and CAD tools and Design of Digital VLSI ICs for On-Line Monitoring of Digital VLSI
Circuits
(Project for the Degree: MS by Research )
The CAD tool has been incorporated in the test flow used in Advanced VLSI Design Laboratory, IIT Kharagpur.
3. Impact of Fairness in Failure Detection and Diagnosis of Discrete Event Systems and application to VLSI Circuits
(Project for the Degree: PhD)
|
Sponsored and Consultancy Projects:
1. Title: Failure Detection and Diagnosis of Fair Distributed Discrete Event Systems and Its
application to VLSI Circuits and Networks.
Sponsor: IIT Guwahati
Budget: 2.8 Lakhs
Duration: 2009-2010
Role: Principal Investigator
2. Title: Design, Development and Verification of Network Specific Intrusion Detection System using Failure
Detection and Diagnosis of Discrete Event Systems.
Sponsor: DIT, New Delhi
Budget: 111.78 Lakhs
Duration: 2009-2011
Role: Co-Principal Investigator
3. Title: Remote Triggered Digital System Laboratory under Remote Triggered Lab.
Sponsor: MHRD, New Delhi
Budget: 49 Lakhs
Duration: 2011-2017
Role: Chief Investigator
4. Title: Development of Framework for Logging and Analysis of Network Traffic to secure IT infrastructure.
Sponsor: MCIT at Manipur University, CS dept. at Guwahati University, IT dept. at Assam University
Budget: 15 Lakhs
Duration: 2009-14
Role: Chief Investigator
5. Title: On line Testing of Complex VLSI Circuits using Failure Detection and Diagnosis Theory of Discrete Event Systems.
Sponsor: DIT, New Delhi
Budget: 124 Lakhs
Duration: 2013-17
Role: Chief Investigator
6. Title: Virtual Lab. Integration (Institute Coordinator IIT Guwahati)
Sponsor: MHRD, New Delhi
Budget: 247 Lakhs
Duration: 2014-
Role: Chief Investigator
7. Title: Information Security Research and Development Centre (ISRDC) under Information Security Education and Awareness (ISEA) Project (Phase-II)
Sponsor: Department of Electronics and Information Technology, Govt. of India
Budget: 344 Lakhs
Duration: 2015-20
Role: Co-Chief Investigator
8. Title: A Software Tool for the Planning and Design of Smart Micro Power Grids
Sponsor: IMPacting Research INnovation and Technology (IMPRINT), MHRD, Govt. of India
Budget: 202Lakhs
Duration: 2017-2019
Role: Co-Investigator
9. Title: Virtual Labs Phase-III
Sponsor: NMICTE under MHRD, Govt. of India
Budget: 15 Crores (total for all the consortium members)
Duration: 2018-2020
Role: National Lab Development Coordinator for Electrical Engineering
10. Title: Formal Methods for Modeling and verification of Intrusion Detection system in wireless Networks
Sponsor: Interdisciplinary Cyber Physical Systems (ICPS) Programme, (DST), Govt. of India, New Delhi
Budget: 34 Lakhs
Duration: (Technically approved subject to financial approval)
Role: Principal Investigator
11. Title: Game Theory Based Intrusion Detection System (IDS) for Cyber Physical System
Sponsor: Interdisciplinary Cyber Physical Systems (ICPS) Programme, (DST), Govt. of India, New Delhi
Budget: 39 Lakhs
Duration: (Technically approved subject to financial approval)
Role: Co-Investigator
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नेविगेशन
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